Cypress CY7C1305BV25 User Manual

CY7C1305BV25  
CY7C1307BV25  
18-Mbit Burst of 4 Pipelined SRAM with  
QDR™ Architecture  
Features  
Functional Description  
• Separate independent Read and Write data ports  
• Supports concurrent transactions  
The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous  
Pipelined SRAMs equipped with QDR architecture. QDR  
architecture consists of two separate ports to access the  
memory array. The Read port has dedicated Data Outputs to  
support Read operations and the Write Port has dedicated  
Data Inputs to support Write operations. QDR architecture has  
separate data inputs and data outputs to completely eliminate  
the need to “turn-around” the data bus required with common  
I/O devices. Access to each port is accomplished through a  
common address bus. Addresses for Read and Write  
addresses are latched on alternate rising edges of the input  
(K) clock. Accesses to the device’s Read and Write ports are  
completely independent of one another. In order to maximize  
data throughput, both Read and Write ports are equipped with  
Double Data Rate (DDR) interfaces. Each address location is  
associated with four 18-bit words (CY7C1305BV25) and four  
36-bit words (CY7C1307BV25) that burst sequentially into or  
out of the device. Since data can be transferred into and out  
of the device on every rising edge of both input clocks (K/K and  
C/C) memory bandwidth is maximized while simplifying  
system design by eliminating bus “turn-arounds.”  
• 167-MHz clock for high bandwidth  
• 2.5 ns Clock-to-Valid access time  
• 4-Word Burst for reducing the address bus frequency  
• Double Data Rate (DDR) interfaces on both Read and  
Write Ports (data transferred at 333 MHz) @167 MHz  
• Two input clocks (K and K) for precise DDR timing  
• SRAM uses rising edges only  
• Two input clocks for output data (C and C) to minimize  
clock-skew and flight-time mismatches.  
• Single multiplexed address input bus latches address  
inputs for both Read and Write ports  
• Separate Port Selects for depth expansion  
• Synchronous internally self-timed writes  
• 2.5V core power supply with HSTL Inputs and Outputs  
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)  
• Variable drive HSTL output buffers  
Depth expansion is accomplished with Port Selects for each  
port. Port selects allow each port to operate independently.  
All synchronous inputs pass through input registers controlled  
by the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Expanded HSTL output voltage (1.4V–1.9V)  
• JTAG interface  
Configurations  
• CY7C1305BV25 – 1M x 18  
• CY7C1307BV25 – 512K x 36  
Cypress Semiconductor Corporation  
Document #: 38-05630 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 3, 2006  
CY7C1305BV25  
CY7C1307BV25  
\
Pin Configuration  
165-ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1305BV25 (1M x 18)  
1
2
3
4
5
BWS  
NC  
A
6
7
NC  
BWS  
A
8
9
A
10  
GND/ 72M  
NC  
11  
NC  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
A
B
C
D
E
F
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
GND/ 144M NC/ 36M  
WPS  
A
K
RPS  
A
1
Q9  
NC  
D9  
D10  
Q10  
Q11  
D12  
Q13  
VDDQ  
D14  
Q14  
D15  
D16  
Q16  
Q17  
A
K
NC  
NC  
NC  
NC  
NC  
NC  
VDDQ  
NC  
NC  
NC  
NC  
NC  
NC  
A
0
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VSS  
A
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VSS  
A
Q7  
D11  
NC  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
A
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
A
NC  
D6  
Q12  
D13  
VREF  
NC  
NC  
G
H
J
NC  
VREF  
Q4  
K
L
NC  
D3  
Q15  
NC  
NC  
M
N
P
R
Q1  
D17  
NC  
NC  
A
C
A
D0  
TCK  
A
A
C
A
A
TMS  
CY7C1307BV25 (512K x 36)  
1
2
3
4
5
BWS  
BWS  
A
6
7
BWS  
BWS  
A
8
9
10  
11  
NC  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
A
B
C
D
E
F
NC  
GND/ 288M NC/ 72M WPS  
K
RPS  
A
NC/ 36M GND/ 144M  
2
3
1
0
Q27  
D27  
D28  
Q29  
Q30  
D30  
NC  
Q18  
Q28  
D20  
D29  
Q21  
D22  
VREF  
Q31  
D32  
Q24  
Q34  
D26  
D35  
TCK  
D18  
D19  
Q19  
Q20  
D21  
Q22  
VDDQ  
D23  
Q23  
D24  
D25  
Q25  
Q26  
A
A
K
D17  
D16  
Q16  
Q15  
D14  
Q13  
VDDQ  
D12  
Q12  
D11  
D10  
Q10  
Q9  
Q17  
Q7  
VSS  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VSS  
A
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
A
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
A
D15  
D6  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
Q14  
D13  
VREF  
Q4  
G
H
J
D31  
Q32  
Q33  
D33  
D34  
Q35  
TDO  
K
L
D3  
Q11  
Q1  
M
N
P
R
VSS  
D9  
A
A
C
A
D0  
A
A
C
A
A
A
TMS  
Document #: 38-05630 Rev. *A  
Page 3 of 21  
CY7C1305BV25  
CY7C1307BV25  
Pin Definitions  
Name  
I/O  
Description  
Data input signals, sampled on the rising edge of K and K clocks during valid write  
D
Input-  
[x:0]  
Synchronous operations.  
CY7C1305BV25 – D  
[17:0]  
[35:0]  
CY7C1307BV25 – D  
WPS  
Input-  
Synchronous asserted active, a Write operation is initiated. Deasserting will deselect the Write port.  
Deselecting the Write port will cause D to be ignored.  
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When  
[x:0]  
BWS , BWS ,  
Input-  
Byte Write Select 0, 1, 2, and 3–active LOW. Sampled on the rising edge of the K and  
0
1
3
BWS , BWS  
Synchronous K clocks during Write operations. Used to select which byte is written into the device  
during the current portion of the Write operations. Bytes not written remain unaltered.  
2
CY7C1305BV25 - BWS controls D  
and BWS controls D  
0
[8:0]  
[8:0]  
1
[17:9].  
, BWS controls D  
CY7C1307BV25 - BWS controls D  
, BWS controls D  
0
1
[17:9] [26:18]  
2
and BWS controls D  
3
[35:27]  
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a  
Byte Write Select will cause the corresponding byte of data to be ignored and not written  
into the device.  
A
Input-  
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write  
Synchronous operations. These address inputs are multiplexed for both Read and Write operations.  
Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for  
CY7C1305BV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307BV25.  
Therefore, only 18 address inputs for CY7C1305BV25 and 17 address inputs for  
CY7C1307BV25. These inputs are ignored when the appropriate port is deselected.  
Q
Outputs-  
Data Output signals. These pins drive out the requested data during a Read operation.  
[x:0]  
Synchronous Valid data is driven out on the rising edge of both the C and C clocks during Read  
operations or K and K when in single clock mode. When the Read port is deselected,  
Q
are automatically three-stated.  
[x:0]  
CY7C1305BV25 - Q  
CY7C1307BV25 - Q  
[17:0]  
[35:0]  
RPS  
Input-  
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).  
Synchronous When active, a Read operation is initiated. Deasserting will cause the Read port to be  
deselected. When deselected, the pending access is allowed to complete and the output  
drivers are automatically three-stated following the next rising edge of the C clock. Each  
read access consists of a burst of four sequential 18-bit or 36-bit transfers.  
C
C
K
Input-Clock  
Input-Clock  
Input-Clock  
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the  
Read data from the device. C and C can be used together to deskew the flight times of  
various devices on the board back to the controller. See application example for further  
details.  
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the  
Read data from the device. C and C can be used together to deskew the flight times of  
various devices on the board cack to the controller. See application example for further  
details.  
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs  
to the device and to drive out data through Q  
when in single clock mode. All accesses  
[x:0]  
are initiated on the rising edge of K.  
K
Input-Clock  
Input  
Negative Input Clock Input. K is used to capture synchronous inputs to the device and  
to drive out data through Q when in single clock mode.  
[x:0]  
ZQ  
Output Impedance Matching Input. This input is used to tune the device outputs to the  
system data bus impedance. Q output impedance are set to 0.2 x RQ, where RQ is  
[x:0]  
a resistor connected between ZQ and ground. Alternately, this pin can be connected  
directly to V , which enables the minimum impedance mode. This pin cannot be  
DDQ  
connected directly to VSS or left unconnected.  
TDO  
TCK  
TDI  
Output  
Input  
Input  
Input  
TDO pin for JTAG  
TCK pin for JTAG  
TDI pin for JTAG  
TMS  
TMS pin for JTAG  
Document #: 38-05630 Rev. *A  
Page 4 of 21  
CY7C1305BV25  
CY7C1307BV25  
Pin Definitions (continued)  
Name  
NC/36M  
I/O  
Description  
N/A  
Address expansion for 36M. This is not connected to the die. Can be connected to any  
voltage level on CY7C1305BV25/CY7C1307BV25.  
GND/72M  
NC/72M  
Input  
N/A  
Address expansion for 72M. This should be tied LOW on the CY7C1305BV25.  
Address expansion for 72M. This can be connected to any voltage level on  
CY7C1307BV25.  
GND/144M  
GND/288M  
Input  
Input  
Address expansion for 144M. This should be tied LOW on  
CY7C1305BV25/CY7C1307BV25.  
Address expansion for 144M. This should be tied LOW on CY7C1307BV25.  
V
Input-  
Reference  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs  
and Outputs as well as AC measurement points.  
REF  
V
V
V
Power Supply Power supply inputs to the core of the device  
Ground Ground for the device  
Power Supply Power supply inputs for the outputs of the device  
N/A Not connected to the die. Can be tied to any voltage level.  
subsequent rising edge of C the next 18-bit data word is driven  
onto the Q . This process continues until all four 18-bit data  
DD  
SS  
DDQ  
NC  
Introduction  
[17:0]  
Functional Overview  
words have been driven out onto Q  
. The requested data  
[17:0]  
will be valid 2.5 ns from the rising edge of the output clock  
(C and C, or K and K when in single clock mode, 250-MHz  
device). In order to maintain the internal logic, each Read  
access must be allowed to complete. Each Read access  
consists of four 18-bit data words and takes 2 clock cycles to  
complete. Therefore, Read accesses to the device can not be  
initiated on two consecutive K clock rises. The internal logic of  
the device will ignore the second Read request. Read  
accesses can be initiated on every other K clock rise. Doing  
so will pipeline the data flow such that data is transferred out  
of the device on every rising edge of the output clocks (C and  
C, or K and K when in single clock mode).  
The CY7C1305BV25/CY7C1307BV25 are synchronous  
pipelined Burst SRAMs equipped with both a Read port and a  
Write port. The Read port is dedicated to Read operations and  
the Write Port is dedicated to Write operations. Data flows into  
the SRAM through the Write port and out through the Read  
port. These devices multiplex the address inputs in order to  
minimize the number of address pins required. By having  
separate Read and Write ports, the device completely elimi-  
nates the need to “turn-around” the data bus and avoids any  
possible data contention, thereby simplifying system design.  
Each access consists of four 18-bit data transfers in the case  
of CY7C1305BV25 and four 36-bit data transfers in the case  
of CY7C1307BV25, in two clock cycles.  
When the read port is deselected, the CY7C1305BV25 will first  
complete the pending read transactions. Synchronous internal  
circuitry will automatically three-state the outputs following the  
next rising edge of the positive output clock (C). This will allow  
for a seamless transition between devices without the  
insertion of wait states in a depth expanded memory.  
Accesses for both ports are initiated on the rising edge of the  
positive input clock (K). All synchronous input timing is refer-  
enced from the rising edge of the input clocks (K and K) and  
all output timing is referenced to the rising edge of output  
clocks (C and C, or K and K when in single clock mode).  
Write Operations  
All synchronous data inputs (D  
) pass through input  
[x:0]  
registers controlled by the rising edge of input clocks (K and  
K). All synchronous data outputs (Q ) pass through output  
registers controlled by the rising edge of the output clocks (C  
Write operations are initiated by asserting WPS active at the  
rising edge of the positive input clock (K). On the following K  
[x:0]  
clock rise the data presented to D  
is latched and stored  
[17:0]  
and C, or K and K when in single clock mode).  
into the lower 18-bit Write Data register provided BWS  
are  
[1:0]  
both asserted active. On the subsequent rising edge of the  
All synchronous control (RPS, WPS, BWS  
through input registers controlled by the rising edge of input  
clocks (K and K).  
) inputs pass  
[0:x]  
negative input clock (K) the information presented to D  
also stored into the Write Data Register provided BWS  
is  
are  
[17:0]  
[1:0]  
both asserted active. This process continues for one more  
cycle until four 18-bit words (a total of 72 bits) of data are  
stored in the SRAM. The 72 bits of data are then written into  
the memory array at the specified location. Therefore, Write  
accesses to the device can not be initiated on two consecutive  
K clock rises. The internal logic of the device will ignore the  
second Write request. Write accesses can be initiated on  
every other rising edge of the positive clock (K). Doing so will  
pipeline the data flow such that 18-bits of data can be trans-  
ferred into the device on every rising edge of the input clocks  
(K and K).  
CY7C1305BV25 is described in the following sections. The  
same basic descriptions apply to CY7C1307BV25.  
Read Operations  
The CY7C1305BV25 is organized internally as 4 arrays of  
256K x 18. Accesses are completed in a burst of four  
sequential 18-bit data words. Read operations are initiated by  
asserting RPS active at the rising edge of the Positive Input  
Clock (K). The address presented to Address inputs are stored  
in the Read address register. Following the next K clock rise  
the corresponding lowest order 18-bit word of data is driven  
onto the Q  
using C as the output timing reference. On the  
[17:0]  
Document #: 38-05630 Rev. *A  
Page 5 of 21  
CY7C1305BV25  
CY7C1307BV25  
When deselected, the write port will ignore all inputs after the  
pending Write operations have been completed.  
includes forwarding data from a Write cycle that was initiated  
on the previous K clock rise.  
Read and Write accesses must be scheduled such that one  
transaction is initiated on any clock cycle. If both ports are  
selected on the same K clock rise, the arbitration depends on  
the previous state of the SRAM. If both ports were deselected,  
the Read port will take priority. If a Read was initiated on the  
previous cycle, the Write port will assume priority (since Read  
operations can not be initiated on consecutive cycles). If a  
Write was initiated on the previous cycle, the Read port will  
assume priority (since Write operations can not be initiated on  
consecutive cycles). Therefore, asserting both port selects  
active from a deselected state will result in alternating  
Read/Write operations being initiated, with the first access  
being a Read.  
Byte Write Operations  
Byte Write operations are supported by the CY7C1305BV25.  
A write operation is initiated as described in the Write  
Operation section above. The bytes that are written are deter-  
mined by BWS and BWS , which are sampled with each set  
0
1
of 18-bit data word. Asserting the appropriate Byte Write  
Select input during the data portion of a write will allow the data  
being presented to be latched and written into the device.  
Deasserting the Byte Write Select input during the data portion  
of a write will allow the data stored in the device for that byte  
to remain unaltered. This feature can be used to simplify  
Read/Modify/Write operations to a Byte Write operation.  
Single Clock Mode  
Depth Expansion  
The CY7C1305BV25 can be used with a single clock that  
controls both the input and output registers. In this mode the  
device will recognize only a single pair of input clocks (K and  
K) that control both the input and output registers. This  
operation is identical to the operation if the device had zero  
skew between the K/K and C/C clocks. All timing parameters  
remain the same in this mode. To use this mode of operation,  
the user must tie C and C HIGH at power-on. This function is  
a strap option and not alterable during device operation.  
The CY7C1305BV25 has a Port Select input for each port.  
This allows for easy depth expansion. Both Port Selects are  
sampled on the rising edge of the positive input clock only (K).  
Each port select input can deselect the specified port.  
Deselecting a port will not affect the other port. All pending  
transactions (Read and Write) will be completed prior to the  
device being deselected.  
Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ  
Concurrent Transactions  
pin on the SRAM and V to allow the SRAM to adjust its  
SS  
The Read and Write ports on the CY7C1305BV25 operate  
completely independently of one another. Since each port  
latches the address inputs on different clock edges, the user  
can Read or Write to any location, regardless of the trans-  
action on the other port. If the ports access the same location  
at the same time, the SRAM will deliver the most recent infor-  
mation associated with the specified address location. This  
output driver impedance. The value of RQ must be 5X the  
value of the intended line impedance driven by the SRAM, The  
allowable range of RQ to guarantee impedance matching with  
a tolerance of ±15% is between 175and 350, with  
V
=1.5V. The output impedance is adjusted every 1024  
DDQ  
cycles upon power-up to account for drifts in supply voltage  
and temperature.  
Application Example[1]  
Note:  
1. The above application shows four QDR-I being used.  
Document #: 38-05630 Rev. *A  
Page 6 of 21  
CY7C1305BV25  
CY7C1307BV25  
Truth Table[2, 3, 4, 5, 6, 7, 8, 9]  
Operation  
K
RPS WPS  
DQ  
DQ  
DQ  
DQ  
[8]  
[9]  
Write Cycle:  
L-H  
H
L
D(A+00) at  
D(A+01) at  
D(A+10) at  
D(A+11) at  
Load address on the rising  
edge of K; wait one cycle;  
input write data on two  
consecutive K and K rising  
edges.  
K(t+1) ↑  
K(t+1) ↑  
K(t+2) ↑  
K(t+2) ↑  
[9]  
Read Cycle:  
L-H  
L-H  
L
X
Q(A+00) at  
C(t+1) ↑  
Q(A+01) at  
C(t+1) ↑  
Q(A+10) at  
C(t+2) ↑  
Q(A+11) at  
C(t+2) ↑  
Load address on the rising  
edge of K; wait one cycle;  
read data on two consec-  
utive C and C rising edges.  
NOP: No operation  
H
H
X
D = X  
Q = High-Z  
D = X  
Q = High-Z  
D = X  
Q = High-Z  
D = X  
Q = High-Z  
Standby: Clock stopped  
Stopped  
X
Previous state  
Previous state  
Previous state  
Previous state  
Write Cycle Descriptions (CY7C1305BV25)[2, 10]  
BWS  
BWS  
K
L-H  
K
Comments  
0
1
L
L
L
L
L
During the Data portion of a Write sequence, both bytes (D  
) are written into the device.  
[17:0]  
L-H During the Data portion of a Write sequence, both bytes (D  
) are written into the device.  
[17:0]  
H
L-H  
During the Data portion of a Write sequence, only the lower byte (D  
) is written into the  
[8:0]  
device. D  
will remain unaltered.  
[17:9]  
L
H
H
H
H
L
L
L-H  
L-H During the Data portion of a Write sequence, only the lower byte (D  
device. D will remain unaltered.  
) is written into the  
[8:0]  
[17:9]  
During the Data portion of a Write sequence, only the upper byte (D  
) is written into  
) is written into  
[17:9]  
the device. D  
will remain unaltered.  
[8:0]  
L-H During the Data portion of a Write sequence, only the upper byte (D  
the device. D will remain unaltered.  
[17:9]  
[8:0]  
H
H
L-H  
No data is written into the device during this portion of a Write operation.  
H
L-H No data is written into the device during this portion of a Write operation.  
Notes:  
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, represents rising edge.  
3. Device will power-up deselected and the outputs in a three-state condition.  
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst.  
5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.  
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.  
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging  
symmetrically.  
8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.  
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will  
ignore the second Read request.  
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS and BWS in the case of CY7C1305BV25 and BWS and BWS in  
0
1
2
3
the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.  
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CY7C1305BV25  
CY7C1307BV25  
[2, 10]  
Write Cycle Descriptions (CY7C1307BV25)  
BWS  
BWS  
BWS  
BWS  
3
K
K
Comments  
During the Data portion of a Write sequence, all four bytes  
(D ) are written into the device.  
0
1
2
L
L
L
L
L-H  
[35:0]  
L
L
L
L
L
L-H  
During the Data portion of a Write sequence, all four bytes  
(D ) are written into the device.  
[35:0]  
H
H
H
L-H  
During the Data portion of a Write sequence, only the lower  
byte (D ) is written into the device. D will remain  
[8:0]  
[35:9]  
unaltered.  
During the Data portion of a Write sequence, only the lower  
byte (D ) is written into the device. D will remain  
L
H
L
H
H
H
L
H
H
H
H
H
L
L-H  
L-H  
[8:0]  
[35:9]  
unaltered.  
During the Data portion of a Write sequence, only the byte  
(D ) is written into the device. D and D will  
H
H
H
H
H
H
[17:9]  
[8:0]  
[35:18]  
remain unaltered.  
During the Data portion of a Write sequence, only the byte  
(D ) is written into the device. D and D will  
L
L-H  
[17:9]  
[8:0]  
[35:18]  
remain unaltered.  
During the Data portion of a Write sequence, only the byte  
(D ) is written into the device. D and D will  
H
H
H
H
L-H  
[26:18]  
[17:0]  
[35:27]  
remain unaltered.  
During the Data portion of a Write sequence, only the byte  
(D ) is written into the device. D and D will  
L
L-H  
[26:18]  
[17:0]  
[35:27]  
remain unaltered.  
During the Data portion of a Write sequence, only the byte  
(D ) is written into the device. D will remain  
H
H
L-H  
[35:27]  
[26:0]  
unaltered.  
During the Data portion of a Write sequence, only the byte  
(D ) is written into the device. D will remain  
L
L-H  
[35:27]  
[26:0]  
unaltered.  
H
H
H
H
H
H
H
H
L-H  
No data is written into the device during this portion of a Write  
operation.  
L-H  
No data is written into the device during this portion of a write  
operation.  
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CY7C1305BV25  
CY7C1307BV25  
TDI and TDO pins as shown in TAP Controller Block Diagram.  
Upon power-up, the instruction register is loaded with the  
IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
These SRAMs incorporate a serial boundary scan test access  
port (TAP) in the FBGA package. This part is fully compliant  
with IEEE Standard #1149.1-1900. The TAP operates using  
JEDEC standard 2.5V I/O logic levels.  
When the TAP controller is in the Capture IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board level serial test path.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
Bypass Register  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
nally pulled up and may be unconnected. They may alternately  
SS  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
be connected to V  
through a pull-up resistor. TDO should  
DD  
be left unconnected. Upon power-up, the device will come up  
in a reset state which will not interfere with the operation of the  
device.  
(V ) when the BYPASS instruction is executed.  
SS  
Test Access Port—Test Clock  
Boundary Scan Register  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
The boundary scan register is connected to all of the input and  
output pins on the SRAM. Several no connect (NC) pins are  
also included in the scan register to reserve pins for higher  
density devices.  
Test Mode Select  
The boundary scan register is loaded with the contents of the  
RAM Input and Output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and  
TDO pins when the controller is moved to the Shift-DR state.  
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-  
tions can be used to capture the contents of the Input and  
Output ring.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this pin unconnected if the TAP is not used. The pin is  
pulled up internally, resulting in a logic HIGH level.  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. For  
information on loading the instruction register, see the TAP  
Controller State Diagram. TDI is internally pulled up and can  
be unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) on any register.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI, and the LSB is connected to TDO.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
Test Data-Out (TDO)  
The TDO output pin is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine (see Instruction codes). The  
output changes on the falling edge of TCK. TDO is connected  
to the least significant bit (LSB) of any register.  
TAP Instruction Set  
Performing a TAP Reset  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the  
Instruction Code table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
A Reset is performed by forcing TMS HIGH (V ) for five rising  
DD  
edges of TCK. This RESET does not affect the operation of  
the SRAM and may be performed while the SRAM is  
operating. At power-up, the TAP is reset internally to ensure  
that TDO comes up in a high-Z state.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO pins.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
TAP Registers  
Registers are connected between the TDI and TDO pins and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction registers. Data is serially loaded into the TDI pin  
on the rising edge of TCK. Data is output on the TDO pin on  
the falling edge of TCK.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO pins and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state. The IDCODE instruction  
Instruction Register  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
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CY7C1305BV25  
CY7C1307BV25  
is loaded into the instruction register upon power-up or  
whenever the TAP controller is given a test logic reset state.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO pins. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High-Z state until the next command is  
given during the “Update IR” state.  
EXTEST  
The EXTEST instruction enables the preloaded data to be  
driven out through the system output pins. This instruction also  
selects the boundary scan register to be connected for serial  
access between the TDI and TDO in the shift-DR controller  
state.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
EXTEST Output Bus Tri-state  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 10 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
will undergo a transition. The TAP may then try to capture a  
signal while in transition (metastable state). This will not harm  
the device, but there is no guarantee as to the value that will  
be captured. Repeatable results may not be possible.  
IEEE Standard 1149.1 mandates that the TAP controller be  
able to put the output bus into a tri-state mode.  
The boundary scan register has a special bit located at bit #47.  
When this scan cell, called the “extest output bus tri-state”, is  
latched into the preload register during the “Update-DR” state  
in the TAP controller, it will directly control the state of the  
output (Q-bus) pins, when the EXTEST is entered as the  
current instruction. When HIGH, it will enable the output  
buffers to drive the output bus. When LOW, this bit will place  
the output bus into a High-Z condition.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that  
cell, during the “Shift-DR” state. During “Update-DR”, the value  
loaded into that shift-register cell will latch into the preload  
register. When the EXTEST instruction is entered, this bit will  
directly control the output Q-bus pins. Note that this bit is  
pre-set HIGH to enable the output when the device is  
powered-up, and also when the TAP controller is in the  
Test-Logic-Reset” state.  
hold times (t and t ). The SRAM clock input might not be  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO pins.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells  
prior to the selection of another boundary scan test operation.  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
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CY7C1305BV25  
CY7C1307BV25  
TAP Controller State Diagram[11]  
TEST-LOGIC  
1
RESET  
0
1
1
1
TEST-LOGIC/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
1
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
Note:  
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
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Page 11 of 21  
CY7C1305BV25  
CY7C1307BV25  
TAP Controller Block Diagram  
0
Bypass Register  
Selection  
TDI  
Selection  
Circuitry  
2
1
0
0
0
TDO  
Circuitry  
Instruction Register  
29  
31 30  
.
.
2
1
Identification Register  
.
106 .  
.
.
2
1
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
[12, 15, 17]  
TAP Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Test Conditions  
= 2.0 mA  
= 100 µA  
= 2.0 mA  
Min.  
1.7  
Max.  
Unit  
V
V
I
I
I
I
OH1  
OH2  
OL1  
OL2  
IH  
OH  
OH  
OL  
OL  
V
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
2.1  
V
0.7  
0.2  
V
= 100 µA  
V
1.7  
–0.3  
5  
V
+ 0.3  
V
DD  
Input LOW Voltage  
0.7  
5
V
IL  
Input and Output Load Current  
GND V V  
µA  
X
I
DDQ  
[13, 14]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Description  
Min.  
Max.  
Unit  
ns  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
50  
TCYC  
20  
MHz  
ns  
TF  
TH  
TL  
20  
20  
TCK Clock LOW  
ns  
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
10  
10  
10  
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
10  
10  
10  
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes:  
12. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.  
13. Parameters t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
14. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.  
R
F
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CY7C1305BV25  
CY7C1307BV25  
[13, 14]  
TAP AC Switching Characteristics Over the Operating Range (continued)  
Parameter  
Description  
Min.  
Max.  
Unit  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
20  
ns  
ns  
TDOV  
TDOX  
0
TAP Timing and Test Conditions[14]  
1.25V  
50Ω  
ALL INPUT PULSES  
1.25V  
TDO  
2.5V  
Z =50Ω  
0
C = 20 pF  
L
0V  
t
GND  
TL  
t
(a)  
TH  
Test Clock  
TCK  
t
TCYC  
t
TMSS  
t
TMSH  
Test Mode Select  
TMS  
t
TDIS  
t
TDIH  
Test Data-In  
TDI  
Test Data-Out  
TDO  
t
t
TDOX  
TDOV  
Identification Register Definitions  
Value  
Instruction Field  
Revision Number (31:29)  
Cypress Device ID (28:12)  
Cypress JEDEC ID (11:1)  
ID Register Presence (0)  
CY7C1305BV25  
000  
CY7C1307BV25  
Description  
000  
Version number.  
01011010011010101 01011010011100101 Defines the type of SRAM.  
00000110100  
1
00000110100  
1
Allows unique identification of SRAM vendor.  
Indicate the presence of an ID register.  
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Page 13 of 21  
CY7C1305BV25  
CY7C1307BV25  
Scan Register Sizes  
Register Name  
Instruction  
Bit Size  
3
1
Bypass  
ID  
32  
107  
Boundary Scan  
Instruction Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the Input/Output ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI and TDO.  
This operation does not affect SRAM operation.  
SAMPLE Z  
010  
Captures the Input/Output contents. Places the boundary scan register between TDI and  
TDO. Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the Input/Output ring contents. Places the boundary scan register between TDI  
and TDO. Does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operation.  
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CY7C1305BV25  
CY7C1307BV25  
Boundary Scan Order  
Bit #  
0
Bump ID  
6R  
Bit #  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
Bump ID  
11H  
10G  
9G  
Bit #  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Bump ID  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
1H  
1A  
2B  
3B  
1C  
1B  
3D  
3C  
1D  
2C  
3E  
2D  
2E  
1E  
2F  
Bit #  
81  
Bump ID  
3G  
2G  
1J  
1
6P  
82  
2
6N  
83  
3
7P  
11F  
11G  
9F  
84  
2J  
4
7N  
85  
3K  
3J  
5
7R  
86  
6
8R  
10F  
11E  
10E  
10D  
9E  
87  
2K  
1K  
2L  
7
8P  
88  
8
9R  
89  
9
11P  
10P  
10N  
9P  
90  
3L  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
91  
1M  
1L  
10C  
11D  
9C  
92  
93  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
10M  
11N  
9M  
94  
9D  
95  
11B  
11C  
9B  
96  
9N  
97  
11L  
11M  
9L  
98  
10B  
11A  
Internal  
9A  
99  
100  
101  
102  
103  
104  
105  
106  
10L  
11K  
10K  
9J  
8B  
7C  
9K  
6C  
3F  
10J  
11J  
8A  
1G  
1F  
7A  
Document #: 38-05630 Rev. *A  
Page 15 of 21  
CY7C1305BV25  
CY7C1307BV25  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired.)  
Storage Temperature ................................ –65°C to + 150°C  
Latch-Up Current................................................... > 200 mA  
Ambient Temperature with  
Power Applied............................................55°C to + 125°C  
Operating Range  
Supply Voltage on V Relative to GND....... –0.5V to + 3.6V  
DD  
Ambient  
Range Temperature (T  
[16]  
[16]  
V
DDQ  
Supply Voltage on V  
Relative to GND .....0.5V to + V  
V
DD  
DDQ  
DD  
A)  
DC Applied to Outputs in High-Z State –0.5V to V  
+ 0.5V  
Com’l  
Ind’l  
0°C to +70°C  
2.5 ± 0.1V  
1.4V to 1.9V  
DDQ  
[15]  
DC Input Voltage ...............................–0.5V to V + 0.5V  
–40°C to +85°C  
DD  
[17]  
Electrical Characteristics Over the Operating Range  
DC Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
2.4  
Typ.  
Max.  
Unit  
V
V
V
V
V
V
V
V
V
I
2.5  
1.5  
2.6  
DD  
1.4  
1.9  
V
DDQ  
OH  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Note 18  
Note 19  
V
V
/2 – 0.12  
/2 – 0.12  
V
V
/2 + 0.12  
/2 + 0.12  
V
DDQ  
DDQ  
DDQ  
DDQ  
V
OL  
I
I
= –0.1 mA, Nominal Impedance  
= 0.1 mA, Nominal Impedance  
V
– 0.2  
V
DDQ  
V
OH(LOW)  
OL(LOW)  
IH  
OH  
OH  
DDQ  
V
0.2  
+ 0.3  
DDQ  
V
SS  
[15]  
Input HIGH Voltage  
V
+ 0.1  
V
V
REF  
[15, 20]  
Input LOW Voltage  
–0.3  
V
– 0.1  
V
IL  
REF  
Input Load Current  
GND V V  
–5  
–5  
5
µA  
µA  
V
X
I
DDQ  
I
Output Leakage Current  
Input Reference Voltage  
GND V V  
Output Disabled  
5
OZ  
I
DDQ,  
[21]  
V
Typical value = 0.75V  
0.68  
0.75  
0.95  
400  
REF  
I
V
Operating Supply  
V
= Max., I  
= 0 mA,  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
CYC  
f = f  
MAX  
I
Automatic  
Power-Down  
Current  
Max. V , Both Ports  
200  
mA  
SB1  
DD  
Deselected,V V or V < V  
IN  
IH  
IN  
IL  
f = f  
= 1/t  
Inputs Static  
MAX  
CYC,  
AC Input Requirements Over the Operating Range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
V
V
V
V
+ 0.2  
IH  
IL  
REF  
V
– 0.2  
V
REF  
Thermal Resistance[22]  
165 FBGA  
Package  
Parameter  
Description  
Thermal Resistance  
(Junction to Ambient) dures for measuring thermal impedance, per  
Test Conditions  
Test conditions follow standard test methods and proce-  
Unit  
Θ
16.7  
°C/W  
JA  
EIA/JESD51.  
Θ
Thermal Resistance  
(Junction to Case)  
2.5  
°C/W  
JC  
Notes:  
15. Overshoot: V (AC) < V  
+0.85V (Pulse width less than t  
/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than t  
/2).  
IH  
DDQ  
CYC  
CYC  
16. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
DD  
IH  
DD  
DDQ  
DD  
17. All Voltage referenced to Ground.  
18. Output are impedance controlled. I = –(V  
/2)/(RQ/5) for values of 175<= RQ <= 350.  
OH  
DDQ  
19. Output are impedance controlled. I = (V  
2)/(RQ/5) for values of 175<= RQ <= 350.  
OL  
DDQ/  
20. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V  
– 0.2V.  
IL  
REF  
21. V  
(Min.) = 0.68V or 0.46V  
, whichever is larger, V  
(Max.) = 0.95V or 0.54V  
, whichever is smaller.  
DDQ  
REF  
DDQ  
REF  
22. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05630 Rev. *A  
Page 16 of 21  
CY7C1305BV25  
CY7C1307BV25  
Capacitance[22]  
Parameter  
Description  
Input Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
C
C
C
5
6
7
IN  
A
V
V
= 2.5V.  
DD  
Clock Input Capacitance  
Output Capacitance  
pF  
CLK  
O
= 1.5V  
DDQ  
pF  
AC Test Loads and Waveforms  
V
REF = 0.75V  
0.75V  
VREF  
VREF  
0.75V  
R = 50Ω  
OUTPUT  
[23]  
ALL INPUT PULSES  
Z = 50Ω  
0
OUTPUT  
1.25V  
Device  
R = 50Ω  
L
0.75V  
Under  
Device  
Under  
0.25V  
Test  
5 pF  
VREF = 0.75V  
Slew Rate = 2 V/ns  
ZQ  
Test  
ZQ  
RQ =  
RQ =  
250Ω  
250Ω  
(a)  
(b)  
Document #: 38-05630 Rev. *A  
Page 17 of 21  
CY7C1305BV25  
CY7C1307BV25  
[23]  
Switching Characteristics Over the Operating Range  
167 MHz  
Cypress  
Consortium  
Parameter Parameter  
Description  
Min.  
Max.  
Unit  
[24]  
t
V
(typical) to the First Access Read or Write  
10  
µs  
Power  
CC  
Cycle Time  
t
t
t
t
t
t
t
t
K Clock and C Clock Cycle Time  
Input Clock (K/K and C/C) HIGH  
Input Clock (K/K and C/C) LOW  
6.0  
2.4  
2.4  
2.7  
ns  
ns  
ns  
ns  
CYC  
KH  
KHKH  
KHKL  
KLKH  
KHKH  
KL  
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge  
to rising edge)  
3.3  
2.0  
KHKH  
t
t
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)  
0.0  
ns  
KHCH  
KHCH  
Set-up Times  
t
t
t
t
t
t
Address Set-up to Clock (K and K) Rise  
0.7  
0.7  
0.7  
ns  
ns  
ns  
SA  
SC  
SD  
SA  
SC  
SD  
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS , BWS )  
0
1
D
Set-up to Clock (K and K) Rise  
[x:0]  
Hold Times  
t
t
t
t
Address Hold after Clock (K and K) Rise  
0.7  
0.7  
ns  
ns  
HA  
HC  
HA  
Control Signals Hold after Clock (K and K) Rise  
HC  
(RPS, WPS, BWS , BWS )  
0
1
t
t
D Hold after Clock (K and K) Rise  
[x:0]  
0.7  
ns  
HD  
HD  
Output Times  
[25]  
t
t
t
t
t
t
t
t
C/C Clock Rise (or K/K in single clock mode) to Data Valid  
2.5  
2.5  
ns  
ns  
ns  
ns  
CO  
CHQV  
CHQX  
CHZ  
Data Output Hold after Output C/C Clock Rise (Active to Active)  
1.2  
1.2  
DOH  
CHZ  
CLZ  
[25, 26]  
Clock (C and C) rise to High-Z (Active to High-Z)  
[25, 26]  
Clock (C and C) rise to Low-Z  
CLZ  
Notes:  
23. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,V  
= 0.75V, RQ = 250, V  
= 1.5V, input  
DDQ  
REF  
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.  
OL OH  
24. This part has a voltage regulator that steps down the voltage internally; t  
is the time power needs to be supplied above V minimum initially before a Read  
Power  
DD  
or Write operation can be initiated.  
25. At any given voltage and temperature t  
is less than t  
and, t  
less than t  
.
CHZ  
CLZ  
CHZ  
CO  
26. t  
, t  
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.  
CHZ CLZ  
Document #: 38-05630 Rev. *A  
Page 18 of 21  
CY7C1305BV25  
CY7C1307BV25  
Switching Waveforms[27, 28, 29]  
NOP  
1
READ  
2
WRITE  
3
READ  
4
WRITE  
5
NOP  
7
6
K
t
t
t
t
KH  
KL  
CYC  
KHKH  
K
RPS  
t
t
t
t
SC  
HC  
HC  
SC  
WPS  
A
A0  
A1  
A2  
A3  
t
t
HD  
HD  
t
t
HA  
SA  
t
t
SD  
SD  
D
Q
D10  
D11  
D12  
D13  
D30  
D31  
D32  
D33  
Qx3  
Q00  
Q01  
Q02  
Q03  
Q20  
Q21  
Q22  
Q23  
t
t
KHCH  
CO  
t
DOH  
t
t
t
CLZ  
CHZ  
t
t
CO  
DOH  
C
C
t
t
t
KHCH  
CYC  
KH  
KL  
t
KHKH  
DON’T CARE  
UNDEFINED  
Notes:  
27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.  
28. Outputs are disabled (High-Z) one clock cycle after a NOP.  
29. In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.  
Document #: 38-05630 Rev. *A  
Page 19 of 21  
CY7C1305BV25  
CY7C1307BV25  
Ordering Information  
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered”.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
167  
CY7C1305BV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1307BV25-167BZC  
Commercial  
CY7C1305BV25-167BZXC  
CY7C1307BV25-167BZXC  
CY7C1305BV25-167BZI  
CY7C1307BV25-167BZI  
CY7C1305BV25-167BZXI  
CY7C1307BV25-167BZXI  
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free  
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
Industrial  
165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free  
Package Diagram  
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)  
BOTTOM VIEW  
TOP VIEW  
PIN 1 CORNER  
Ø0.05 M C  
Ø0.25 M C A B  
PIN 1 CORNER  
-0.06  
Ø0.50
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
B
13.00 0.10  
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDECREFERENCE: MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and  
Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05630 Rev. *A  
Page 20 of 21  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1305BV25  
CY7C1307BV25  
Document History Page  
Document Title: CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR™ Architecture  
Document Number: 38-05630  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
253049  
436864  
See ECN  
See ECN  
SYT  
NXR  
New Data Sheet  
*A  
Converted from Preliminary to Final.  
Removed 133 MHz & 100 MHz from product offering.  
Included industrial Operating Range.  
Changed C/C Description in the Features Section & Pin Description Table.  
Changed t  
from 100 ns to 50 ns, changed t from 10 MHz to 20 MHz  
TCYC  
TF  
and changed t and t from 40 ns to 20 ns in TAP AC Switching  
TH  
TL  
Characteristics table  
Modified the ZQ pin definition as follows:  
Alternately, this pin can be connected directly to V  
minimum impedance mode  
, which enables the  
DDQ  
Included Maximum Ratings for Supply Voltage on V  
Relative to GND  
DDQ  
Changed the Maximum Ratings for DC Input Voltage from V  
to V  
DDQ  
DD.  
Modified the Description of I from Input Load current to Input Leakage  
X
Current on page # 16.  
Modified test condition in note# 16 from V  
< V to V  
V  
DDQ  
DD  
DDQ DD  
Updated the Ordering Information table and replaced the Package Name  
Column with Package Diagram.  
Document #: 38-05630 Rev. *A  
Page 21 of 21  

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